Santa Clara, CA (PRWEB) May 23, 2005
VeriEZ Solutions, Inc., the Verification Tools Company, made a strong commitment to SystemVerilog today with the announcement of SystemVerilog support for EZVerify. The EZVerify product provides static analysis and automatic knowledge extraction for OpenVera and SystemVerilog-based verification flows.
The SystemVerilog extension to EZVerify enables customers to reuse existing OpenVera modules with new SystemVerilog development. ÂSolving customer problems remains our top priority,Â said Sashi Obilisetty, President and CEO of VeriEZ Solutions. ÂWe believe our valued customers would like to use our tools in a SystemVerilog environment, and we have made it possible with our current offeringÂ.
EZVerify is equally useful to new users contemplating a switch to SystemVerilog for Verification. EZVerifyÂs static analysis finds errors in verification code, and provides an infrastructure for creating and implementing corporate-wide Hardware Verification Language (HVL) guidelines. As the verification projects increase in complexity, it becomes essential to augment HVL flow with static analysis to detect errors in HVL code as well as to ensure modules are error-free, well documented and reusable.
SystemVerilog Solution Details
EZVerify supports the verification constructs included in the ratified Accellera SystemVerilog standard, popularly known as the SystemVerilog 3.1a, and the emerging IEEE standard (P1800). Its single kernel engine reads and analyzes OpenVera and SystemVerilog modules by loading information into a common object format. It consists of two primary components, EZCheck and EZVerify.
EZCheck static analysis provides new and experienced verification engineers with reports on incorrect concurrency usage, errors in coverage specification and standard lint-type errors such as incompletely assigned functions, loss of bits during assignment and unassigned variables. Further, it allows companies to set up a guideline that encompasses Object Oriented Design principles such as class naming, hierarchy, construct usage and best practices in coding.
EZReport knowledge extraction enables users to view the class hierarchy, class details and port connections of existing libraries and new projects. It provides a proven infrastructure for verification reuse.
Pricing and Availability
The SystemVerilog functionality can be purchased as an option by existing EZVerify customers. U.S list price starts at $20,000 for a one-year, single-language license. SystemVerilog Support will be available to Beta customers in Q4 2005.
EZVerify SystemVerilog product demonstrations can be viewed in VeriEZÂs booth (#355) at DAC (June 13-16, Anaheim).
VeriEZ Solutions, Inc. is a privately held EDA company that develops and markets solutions that enable efficient chip verification. It is the developer of EZVerify and EZTranslate Tool Suites. EZVerify is the industryÂs first mixed-language (OpenVeraÂ®, SystemVerilogÂ®) Productivity Tool Suite. It includes a configurable static lint checker (EZCheck) and a verification knowledge extractor (EZReport). EZTranslate is an OpenVera-to-SystemVerilog migration Tool Suite. VeriEZÂs tools detect errors and enable verification reuse. More information is available on the company website, http://www.veriez.com.
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