IPFlex Introduces PC Acceleration Board DAPDNA-PA1 and Design Tool Improvements

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DAPDNA-PA1 with PCI edge and the latest DAPDNA-FW II design tool with improved third-party tool integration make DRP development easier.

IPFlex Inc. today began sales of the DAPDNA*-PA1, a new PC accelerator board equipped with a DAPDNA-2 dynamically reconfigurable processor** (henceforth referred to as DRP). The DAPDNA-FW II Integrated Development Environment v2.6 is also released with major updates.

The DAPDNA-FW II Integrated Development Environment, with sales of more than 200 licenses as of December 2005, has been upgraded to improve design productivity and enable users to bring products to market even more quickly. DAPDNA-2 is used in an increasing number of commercial systems, and close to a dozen mass production systems powered by DAPDNA-2 is planned for production-start this year. The DAPDNA platform's flexibility in enabling product diversification and reducing development cycles and cost is driving its acceptance in fields such as image processing, networking, security, and research applications.

Major specifications of the DAPDNA-PA1

The DAPDNA-PA1 is a PC accelerator board equipped with the DAPDNA-2 dynamically reconfigurable processor. Connected to the PC via the PCI bus, DAPDNA-PA1 enables efficient development of DAPDNA-2 applications. The DAPDNA-PA1 can be integrated into commercial products, for a significant reduction in development time and cost.

DAPDNA-PA1 Specifications


-DAPDNA-2 x1

On-board devices:

-DDR SDRAM(512MBytes)

-ROM(2Kbits SPI serial ROM for initialization x1, 2Mbits SPI serial ROMs for program storage x4)

-FLASH ROM(16Mbytes)

External interfaces:

-PCI(Card edge connector)

-RS-232C(1 channel)

-Direct I/O(6 channels)


-Device driver(Microsoft Windows XP/2000, Linux support planned)

-Library(Board control library)

-Sample code(Direct I/O sample)

Board size:

-107mm x 210mm

Major new features of DAPDNA-FW II v2.6

The DAPDNA-FW II Integrated Development Environment is a feature-rich set of tools which spans all processes related to development of DAPDNA-2 applications, from algorithm design to verification on the hardware. DAPDNA-FW II supports three different design methodologies: development using Data Flow C (DFC)***, an extended version of the C programming language; development using MATLAB/Simulink****; and development using DNA Designer, a GUI-based component of DAPDNA-FW II which supports graphical interconnection of DAPDNA-2 processing elements. This new release adds an improved level of co-design with MATLAB/Simulink, and adds new library functions that can be called from DFC. The major new features of this release are described below.

1. Cooperation with MATLAB/Simulink

1) Basic Library for MATLAB/Simulink environment added to IPFlex DNA Blockset

The new release adds a Basic Library that can be used in the MATLAB/Simulink environment. There are 14 types of blocks in the new Basic Library. Further, the DNA Library***** supplied with DAPDNA-FW II, is compatible with MATLAB/Simulink, and can be used in MATLAB/Simulink. The addition of the Basic Library brings the total number of available block types to 48.

2) GUI-based Realtime-Link feature

When designing applications to run on DAPDNA-2 using MATLAB/Simulink, it is now possible to use the Simulink environment to directly target either the DAPDNA-FW II Whole Chip Simulator or the actual hardware for real-time execution, debugging, verification, and evaluation.

2. Using DNA Libraries from DFC

The DNA Libraries provided for DNA Designer, one of the design methods supported by DAPDNA-FW II, can now be called from DFC. This feature makes system design with DFC even more efficient.

About the DAPDNA-2 Dynamically Reconfigurable Processor

DAPDNA-2 is a multi-core processor, comprised of a high-performance RISC processor core, called the DAP, and the dynamically reconfigurable core, DNA, a two-dimensional array of 376 processing elements (PEs). DAPDNA-2 can change its hardware configuration to provide the optimal circuitry for an application on demand. This configuration change can take place not only when the system is designed, but also during operation, dynamically, in a single clock cycle******, to meet the instantaneous change in needs of applications implemented by the system.


  • DAPDNA: Digital Application Processor / Distributed Network Architecture.

** Dynamically Reconfigurable Processor (DRP): A processor capable of changing chip circuitry dynamically.

*** DFC: Co-developed with Celoxica Ltd.

**** MATLAB/Simulink: a product developed, marketed, and supported by The MathWorks, Inc.

***** DNA Library: A library of DNA macro blocks for use in DNA Designer.

****** a single clock cycle: One clock switching operation is possible by creating configuration information beforehand and storing in the background configuration banks.

About IPFlex

IPFlex Inc. is a fabless semiconductor company established in March 2000. IPFlex supplies high performance, multifunctional processors that are dynamically reconfigurable, and also provides development software, evaluation boards, and peripheral interface products for the processors. With its DAPDNA dynamically reconfigurable processors and Software-to-Silicon-based DAPDNA-FW II Integrated Development Environment software, IPFlex provides solutions to shorten development cycle and to respond quickly to the changes in applications. IPFlex has focused to provide the optimal solutions for consumer, imaging, wireless, and high-performance applications.

Editors' note: IPFlex, DAPDNA, and Software-to-Silicon are registered trademarks of IPFlex in Japan. Other corporate and product names are the trademarks or registered trademarks of their respective owners.


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