VeriEZ’s SystemVerilog® Static Analysis Technology Put to Unique Use

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Checkers for Verilog® and SystemVerilog Assertion (SVA) users designed to accelerate language usage.

VeriEZ Solutions, Inc., the Verification Tools Company, renewed its commitment to SystemVerilog today with the announcement of two new pre-packaged sets of guidelines (“rulesets”) for design and verification teams. The new rulesets complement existing rulesets in EZVerify, VeriEZ’s productivity solution for OpenVera and SystemVerilog-based design and verification teams. EZVerify utilizes static analysis techniques to provide an environment for creating reusable, object-based and error-free OpenVera and SystemVerilog modules.

“The advantages of static analysis extend far beyond traditional error-detection,” said Sashi Obilisetty, VeriEZ’s President and CEO. “Here we have used our language expertise to minimize the learning curve for design and verification teams interested in utilizing new features in SystemVerilog.”

The new rulesets target two scenarios, Verilog-to-SystemVerilog transition and SystemVerilog Assertions best practices.

Verilog-to-SystemVerilog Ruleset Details

The Verilog-to-SystemVerilog ruleset is designed for engineers currently using Verilog. SystemVerilog offers several valuable features for design teams, such as unambiguous specification for synthesis, interfaces and user-defined data types. It also offers several valuable features for verification teams, such as constrained-random stimulus generation, functional coverage and object-oriented programming support.

One of the biggest hurdles in adopting SystemVerilog is in understanding the new features provided by SystemVerilog, and using these features in an ongoing or legacy project. EZVerify’s Verilog-to-SystemVerilog ruleset can be used as a SystemVerilog guidance tool, where the engineer is informed of Verilog code that can be replaced by newer constructs in SystemVerilog. It includes 15+ checkers that analyze input Verilog and suggest usage of new SystemVerilog constructs. For example, one check performs analysis to determine suitability of new always processes (always_ff, always_comb, always_latch, always_*) in place of the Verilog-compliant ‘always’.

This ruleset addresses the needs of both design and verification teams.

SystemVerilog Assertions Best Practices Ruleset Details

The Assertions ruleset is designed for engineers writing custom assertions. Assertion-based verification (ABV) has been widely adopted by both design and verification teams in recent times. However, custom assertions code can have bugs, performance implications or incompatibility with formal tools. Further, for maximizing reuse, assertions should adhere to pre-determined coding guidelines.

EZVerify’s Assertions ruleset attempts to address the issues arising from ABV implementation using SVA. It contains 20+ rules for checking best practices and for identifying non-synthesizable or low-performance constructs.

Pricing and Availability

New rulesets will be available August 2006 to existing users of EZVerify (SystemVerilog) at no additional charge. EZVerify annual licensing fees starts at $20,000 USD.

VeriEZ product demonstrations, including demonstrations showing the usage of new rulesets, can be viewed in VeriEZ’s booth (#1514) at DAC (July 24-27, 2006, San Francisco).

About VeriEZ

VeriEZ Solutions, Inc. is a privately held EDA company that develops and markets solutions that enable efficient chip verification. It is the developer of EZVerify and EZTranslate Tool Suites. EZVerify is the industry’s first Verification Productivity Tool Suite for OpenVera™ and SystemVerilog®. It includes a configurable static lint checker (EZCheck) and a verification knowledge extractor (EZReport). EZTranslate is an OpenVera-to-SystemVerilog Migration Tool Suite. VeriEZ’s tools detect errors and enable reuse. More information is available on the company website,

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Sashi Obilisetty
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