Helic Launches VeloceWired for Bondwire Design in the IC Flow

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Helic S.A. announces today the commercial release of VeloceWired, a powerful IC package tool that accelerates bondwire design and simulation and enables optimization of high-speed lead-frame packages and co-design with analog and mixed-signal ICs.

Helic S.A. announces today the commercial release of VeloceWired™, a powerful IC package tool that accelerates bondwire design and simulation and enables optimization of high-speed lead-frame packages and co-design with analog and mixed-signal ICs.

With VeloceWired, bondwire design becomes an integral part of the IC tool flow. Featuring a rapid modeling engine that can handle full RLCK extraction of tens of bondwire interconnects in mere seconds, VeloceWired enables the co-design of high-speed circuitry with the package and bridges the related gap in parasitics sign-off. VeloceWired gives IC designers control over the package, and helps them achieve an optimal design down to the pin.

VeloceWired features an efficient and flexible bondwire editor that operates seamlessly in Cadence® Virtuoso®. Bondwires are created in 2-D through a simple point-and-click procedure, while their 3-D properties can be edited on-the-fly. Die-to-die and stacked-die configurations are supported. Additional features include inductance annotation on the layout and persistent bondwire connectivity when moving or rotating the die to achieve optimal placement. At any time, a distributed netlist can be extracted in seconds, capturing complex electromagnetic effects such as self and mutual inductance, frequency-dependent resistance and capacitive coupling from wire to wire and from wire to package.

Sotiris Bantas, Helic's VP of Technology said: "We are proud to announce VeloceWired, a tool that has been long missing from the IC design flow. Customers using our on-chip inductance products have been asking us for a bondwire tool for some time now. So-called 'package design tools' are typically point tools foreign to the IC flow and using them in conjunction with circuit design and simulation is often tedious, error-prone and counter-productive. VeloceWired acts as an extension of custom layout and parasitics extraction and provides excellent accuracy up to several GHz. High-speed and RF IC designers can now afford control over the package that houses their chip, predict all applicable bondwire parasitics and optimize their design from pin to pin. No other alternative comes even close in combining speed, sign-off accuracy and ease-of-use."

VeloceWired complements Helic's product portfolio of inductance-oriented EDA tools, which also comprises VeloceRF™, a market-leading product featuring spiral inductor PCell synthesis and a rapid extraction and verification toolset for inductance-aware RFIC design.

VeloceWired ships as a Cadence Virtuoso plug-in module and takes 5 minutes to install in any PDK. The tool is available immediately and is offered for licensing on a time-based lease basis. For sales enquiries please contact sales@helic.com or visit http://www.helic.com.

About Helic (http://www.helic.com)
Helic S.A. develops disruptive EDA technology for RFIC and System-in-Package design. Its tools have been adopted by several renowned semiconductor companies worldwide. Helic reaches its customers with a service model combining EDA tools, IP and services, aiming to enable first-pass silicon while greatly reducing the development cycles of integrated wireless transceivers.

Editorial Contacts:
Nikolas Provatas
T: +30 2109949390
E: (N.Provatas @ helic.com)

Helic and the Helic logo are registered trademarks of Helic S.A. VeloceRF and VeloceWired are trademarks of Helic S.A. All other marks are property of their respective owners.

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NIKOLAS PROVATAS
Helic SA
+302109949390
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