IP Cores, Inc. Announces an Ultracompact Version of Kasumi Cipher for 3G Devices

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IP Cores, Inc. announces a version of the 3GPP Kasumi cipher with very low gate count and low power consumption.

IP Cores, Inc. has announced availability of a version of Kasumi cipher with very low gate count and power consumption. Along with the ultracompact AES cipher, this core can be used in the new mobile communication devices for 3G networks.

"Innovative design decisions allowed us today to offer to our customers a Kasumi cryptographic core that is about two times smaller than the cores currently on the market," said Dmitri Varsanofiev, CTO of IP Cores. "In the encryption field, power consumption is typically proportional to the number of gates, so this core produces substantial power savings in battery-operated designs."

Ultracompact Encryption Core

The modern mobile data communications standardized through 3GPP typically use for encryption one of the three ciphers: Advanced Encryption Standard (AES), Snow 3G, or Kasumi.

Kasumi block cipher (also known as A5/3) had been designed by SAGE and is used in the f8 and f9 algorithms of the 3GPP data interface. The KSM1 core by IP Cores, Inc. implements the Kasumi encryption algorithm and utilizes only 5.5K gates in a typical 65 nm ASIC process. KSM1 datasheet is available on the IP Cores, Inc. Web site at http://www.ipcores.com/images/Kasumi.pdf .

For more information about IP Cores, Inc.' product line, please visit http://www.ipcores.com .

About IP Cores, Inc.
IP Cores is a rapidly growing company in the field of security and DSP IP cores. Founded 4 years ago, the company provides IP cores for communications and storage fields, including AES-based ECB/CBC/OCB/CFB, AES-GCM and AES-XTS cores, flow-through AES/CCM cores with header parsing for IEEE 802.11 (WiFi), 802.16e (WiMAX), 802.15.3 (MBOA), 802.15.4 (Zigbee), public-key accelerators for RSA and elliptic curve cryptography (ECC), cryptographically secure pseudo-random number generators (CS PRNG), lossless data compression cores as well as low-latency fixed and floating-point FFT, IFFT, and Viterbi detector cores.

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DMITRI VARSANOFIEV
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