BEEcube Targets Wireless and Digital Communications Design Prototyping with BEE3-W Release

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Real World, Real Time, FPGA Based Prototyping

Advanced signal processing algorithms can be rapidly prototyped on the BEE3-W system, running at clock rates of hundreds of MHz, which directly interface to multi-GHz A/D and D/A converters

BEEcube Inc. today announces the immediate availability of BEE3-W™. Specifically designed to address rapid system level prototyping of Wireless and Digital Communications designs, the BEE3-W is based on BEEcube’s successful 3rd generation FPGA (Field Programmable Gate Array) Berkeley Emulation Engine (BEE).

BEE3-W Meets Dynamic Wireless Mission Critical Needs:

With combined ADC and DAC modules and the Xilinx Virtex-5 FPGA based BEE3 hardware platform, BEE3-W enables a wide range of high-performance, real-time implementations in multiple military and defense applications. BEE3-W allows for flexible algorithm and feature set definitions and as a result excels as a true real-time development and deployment platform for:

  • Software Defined Radio (SDR)
  • Signal Intelligence     
  • Wireless (Digital Based RF) Algorithm Applications
  • MIMO Communications
  • Radar Applications

“Advanced signal processing algorithms can be rapidly prototyped on the BEE3-W system, running at clock rates of hundreds of MHz, which directly interface to multi-GHz A/D and D/A converters,” announces Chen Chang, BEEcube’s founder. “When it comes to deployment, the same design can be easily retargeted in the BEEcube Platform Studio (BPS) design environment to fit into various hardware platforms with different form factors, capabilities, and FPGA technologies.”

BEE3-W Hardware Description:

A single BEE3-W system consists of four Xilinx Virtex-5 FPGAs with a capacity of 5M ASIC gates, and the quad FPGA design is interconnected with a ring bus and integrated DDR2-667 memory. Each BEE3-W FPGA follows a symmetrical design, including identical memory and independent I/Os. Multiple high-speed data interfaces include: 160 Gbps SERDES, Quad x8 PCI Express, Quad 1000BASE-T Ethernet, and Quad 40-pair LVDS QSH expansion slots. The system has a capability of buffering 64GB of data in DDR2 memory.

The BEE3-W is integrated with a set ADC and DAC modules. The ADC module has an option of dual channel 3 GSps ADCs with independent clock, data, reset and trigger SMA inputs for each ADC, or a quad channel 1.5 GSps version. The 3Gps boards support 8-bit sampling resolution per channel per ADC/FPGA. The supported analog sample rates range from 1000 to 3000 MHz. The DAC module is a dual 2 GSps model which supports independent clock inputs and data outputs. The sampling resolution can be configured for either 9 bits up to 2 GSps (with a 4:1 mux) or 12 bits up to 1.5 Gsps (with a 2:1 mux).

BEE3-W Offers Easy Algorithm Deployment - BEEcube Platform Studio™ (BPS) Upgraded to Version 3.6:

The BEE3-W system software provides easy deployment of algorithms onto FPGAs. BEEcube Platform Studio™ (BPS), coupled with its high-speed I/O infrastructure, allows algorithm designers without any RTL or implementation knowledge to easily program the target BEE3-W system.

BEEcube Platform Studio (BPS) is a system-level, hardware/software co-development environment built on top of the MathWorks™ Simulink® framework. BPS provides automatic generation of all platform specific hardware interfaces and corresponding software drivers. Months of engineering tasks to convert complex DSP algorithms into an FPGA implementation can be achieved through BPS in a matter of days, all without requiring user knowledge of the low level FPGA implementation details, such as high speed I/O interfaces, timing closure, HW/SW interfaces, and IP integration issues.

With BEE3-W availability, BEEcube Platform Studio is upgraded to version 3.6, which adds several new components to its list of supported hardware/software interfaces. Support is now included for the full range of ADC and DAC modules, which allow users to capture and create real-world analog signals directly within the BPS environment. The inter-FPGA communication interfaces on all BEE3 systems, including BEE3-W, have also been greatly enhanced by the new High Speed I/O component, which provides data transmission speeds up to DDR800 (double data rate signaling at 400MHz clock speed) between FPGAs. This version also adds support for dual-channel DRAM on all BEE3 models, which doubles the amount of memory bandwidth and addressable memory capacity available to each FPGA in the system. In addition, support for DRAM-based video frame buffers has also been added for all BEE3 based models as well as the Xilinx ML50x hardware platform, which delivers a wide range of possibilities in video capture, processing, and generation applications with support for frame buffers up to 4GB in size. As with all previous versions of BPS, each hardware interface comes with full software support via bundled drivers and runtime support in the BEE3 embedded shell.

BEE3-W: A Perfect Platform for Software Defined Radio (SDR) Prototyping and Applications:

BEE3-W comes with an optional SDR based reference design sample. In the design sample, BEE3-W is used to implement a continuous wideband vector signal generator. The BEE3-W prototyping system can handle dynamic carrier frequency tone sweeps ranging anywhere from 0 to 2 GHz. With 2 Gbps of I/O, BEE3-W DACs provide the ability to directly generate wideband analog signals. Coupled with BEE3-W’s ADC modules, simultaneous capture of the analog output signal allows data to be directly presented to the user via standard low-cost algorithm display tools (like Matlab) in real-time, without the need for additional equipment. The ADC reference design can sample at rates up to 3GHz, which provides true direct RF (radio frequency) sampling capability.

About BEEcube:

BEEcube, a leading provider of advanced system-level FPGA prototyping platforms, was founded in 2006. Spinning out of the University of California, Berkeley, BEEcube’s founders include the best academic minds in Silicon Valley and are credited with founding a number of leading companies, including Atheros Communications.

There are over 150 BEE systems deployed worldwide in major corporations and top universities. Corporations currently using BEE systems include: Xilinx, Microsoft, Sun Microsystems, Aerospace Corporation, and Thales Group. Leading universities include: University of California, Berkeley, Stanford University, Massachusetts Institute of Technology, Imperial College London, Barcelona Super Computing Center, Tokyo University, Tsinghua University, and Peking University.

Visit Beecube’s web site at http://www.beecube.com. For more information contact sales(at)beecube(dot)com or phone: 1-510-252-1136. BEEcube’s corporate headquarters is based at 39465 Paseo Padre Parkway, Suite 3700, Fremont, CA 94538.

BEEcube, BEE, BEE3, BEE3-W, BEEcube Platform Studio are trademarks of BEEcube Inc. All rights reserved.

BEEcube acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

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Joseph Rothman