Palo Alto, CA (PRWEB) July 20, 2010
IP Cores, Inc. (http://www.ipcores.com) has announced the first core of its new high-speed IPsec security processor family.
"The new ISP1 core is a self-contained implementation of the IPsec packet encryption and authentication algorithms as defined by the IETF," said Dmitri Varsanofiev, CTO of IP Cores. "Our extensible implementation of the IPsec fits well into the decentralized on-chip processing datapath of the modern routers".
Internet Protocol Security (IPsec) is a protocol used to secure the Internet Protocol (IP) communications by authenticating and/or encrypting IP packets of a data stream.
ISP1 core support both the ESP and AH protocols of IPsec in transport and tunnel modes of operation, including insertion and removal of headers and trailers, padding, Integrity Check Value (ICV) insertion and validation.
ISP supports all encryption algorithms per RFC 4835, including AES-CBC-128, AES-CBC-256, TripleDES-CBC, HMAC-SHA1-96, AES-XCBC-MAC-96. Additional algorithms are available as separate options.
ISP1 datasheet is available on the IP Cores, Inc. Web site at http://ipcores.com/isp1_ipsec_processor_ip_core.htm.
For more information about IP Cores' product line, please visit http://www.ipcores.com.
About IP Cores, Inc.
IP Cores is a rapidly growing company in the field of security, error correction, and DSP IP cores. Founded in 2004, the company provides IP cores for communications and storage fields, including AES-based ECB/CBC/OCB/CFB, AES-GCM and AES-XTS cores, flow-through AES/CCM cores with header parsing for IEEE 802.11 (WiFi), 802.16e (WiMAX), 802.15.3 (MBOA), 802.15.4 (Zigbee), public-key accelerators for RSA and elliptic curve cryptography (ECC), cryptographically secure pseudo-random number generators (CS PRNG), secure SHA and MD5 hashes, lossless data compression cores, low-latency fixed and floating-point FFT and IFFT cores, as well as cyclic, Reed-Solomon, BCH and Viterbi decoder cores.