Our technology breakthrough would make Amdahl’s Wafer Scale Integration dream a reality.
San Jose, CA (PRWEB) December 20, 2011
MonolithIC 3D Inc., a leading 3D-IC company, announced its Ultra-Scale Integration scheme last week. The technology promises to improve the integration level of chips by more than 100x, thereby providing breakthrough performance improvements for supercomputers, servers and many other applications.
Ultra-Scale Integration has been a goal of the semiconductor industry since the 1970s. Gene Amdahl notably attempted to develop Wafer-Scale Integration (WSI) as a method of making a supercomputer, starting Trilogy Systems in 1980 and garnering investments totaling $230 million. After burning through about 1/3 of the capital without finding a path to WSI,Amdahl eventually declared the idea would only work with a 99.99% yield, which wouldn't happen for 100 years. MonolithIC 3D Inc.’s scheme could enable Wafer Scale Integration in the near term.
Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc., said, “Our monolithic 3D technology combined with an effective fine-grained redundancy approach enables defect repair with minimal power and performance overhead. We believe we can make Amdahl’s Ultra-Scale Integration dream a reality. The high levels of integration possible with this scheme could enable a whole new generation of supercomputers, servers and ultra smart electronic products."
The Ultra-Scale Integration scheme builds the same logic circuit twice one on top of the other using 3D stacking approaches. Every fault could be repaired by the replacement logic cone above. Such fine-grained repair should have negligible power and performance penalty since the replacement logic cone is less than 1 micron above the faulty logic cone. As the stacked logic circuits are identical to the original circuits, there is almost no design overhead. Cost penalties are minimal when base circuit yield is about 50% and so the scheme is quite an attractive option for designs which utilize large dice. A dramatic boost in integration is possible because of the yield benefits of fine-grained fault repair. Further details of the scheme are available on the company’s blog.
Moore’s Law has resulted in fast on-chip computation but increasingly costly off-chip communication. nVIDIA’s 28nm chips, for example, utilize 1pJ for an integer add operation but require 16,000pJ for off-chip access. This ratio is projected to get significantly worse with scaling. Due to this, chip makers, and in particular server makers, scramble to integrate as much functionality on a die as possible. The main limitation to large die sizes is yield, which MonolithIC 3D Inc.’s scheme addresses quite effectively.
“We expect to license this technology to high-performance computer system manufacturers first,” noted Brian Cronquist, VP of Technology & IP at MonolithIC 3D Inc. “With scaling progressing to sub-20nm nodes, several manufacturers are plagued with low yields and are looking for schemes to get robust high-yield systems with large numbers of not-so-robust components. Our scheme is an effective solution to this problem.”
About MonolithIC 3D Inc.
MonolithIC 3D Inc. is an IP company dedicated to innovation in semiconductor design and fabrication. It invented and developed a practical path to the monolithic 3D Integrated Circuit, which includes multiple derivatives for Logic, Memory and Electro Optic devices. The company was recently selected as a finalist of the Best of Semicon West 2011, which recognizes the most important product and technology developments at Semicon West. More information about the company, including detailed technical information, can be found at its website.