Announcing Sigasi 2.0 Development

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Sigasi is developing the next version of its popular VHDL development environment. Through a new core, Sigasi HDT 2.0 provides truly interactive feedback to the hardware designer. Within a few weeks, Sigasi will release a fully functional technology demonstrator.

Over one year ago, Sigasi launched its VHDL development environment: Sigasi HDT 1.0. This development environment helps electronics engineers in four critical areas: code comprehension, code reuse, team collaboration and design entry. Its secret sauce is an intelligent, built-in VHDL analyser. As an engineer enters a VHDL design into the environment, Sigasi HDT builds an internal model accurately representing the VHDL code. This knowledge is used to enable quick navigation, suggest improvements, mark errors and generate skeleton code.

Today, students and teachers from hundreds of universities are using Sigasi HDT as a training tool. Professional VHDL designers rely on it for the day-to-day development of medical devices, consumer electronics, automotive and aerospace applications, telecom and defense equipment.

Sigasi's users are a constant source of inspiration as they often come up with new ideas and request innovations. Many requests have been implemented in past releases. Some requests however were not within reach of the current parser core. So, during the past six months, Sigasi have been working on a new parser and analyzer core, based on a family of three industry-standard development platforms: Eclipse, EMF and Xtext.

Although Sigasi are still in the process of porting all existing 1.0 features to the new platform, there are already some noticeable benefits. Probably the most spectacular (and most asked for) feature is type time parsing. This means that Sigasi HDT 2.0 will check the VHDL syntax while the user is are typing, without the need to save the files before getting feedback. A second important feature is that the code completion suggestions are now fully aware of their context. Engineers will get accurate suggestions and they will be more relevant to what they are typing. A final substantial improvement is speed. Sigasi's 2.0 core caches its compilation results on disk, so upon opening an existing project, Sigasi 2.0 will not have to re-parse all of the files.

The new Sigasi HDT 2.0 core will allow the technology to grow faster. It will make it possible to implement new languages (read: Verilog) and will allow Sigasi to efficiently add new and complex linting rules, quickfixes and code refactorings. Sigasi HDT 2.0 is completely extensible, customizable, built on industry standard technology and future proof.

In the next month, Sigasi will release a tech preview for the brave and tech savvy. The first commercial-ready version is expected in the third quarter of 2011. Interested users are invited to visit http://www.sigasi.com/sigasi-hdt-2.0-preview for a short screen cast and to register for the newsletter.

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Philippe Faes
philippe.faes@sigasi.com
+32 9 265 71 38
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