Crack Semiconductor Announces Customer Acceptance for the CS1024 Public Key Accelerator in Banking Applications

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The most demanding security application is found in payment. Literally billions of dollars of transactions are conducted electronically every day and this is only possible through public key security algorithms. Crack Semiconductor is pleased to announce that after rigorous acceptance testing, the CS1024-RSA public key accelerator has been approved for use in a demanding payment application by a leading EU company.

“We are very pleased to have passed the acceptance testing in this demanding payment application,” said Art Low, President and CTO of Crack Semiconductor. “We worked very closely with the customer over the last nine months to deliver the first engine...

The most demanding security application is found in payment. Literally billions of dollars of transactions are conducted electronically every day and this is only possible through public key security algorithms. Crack Semiconductor is pleased to announce that after rigorous acceptance testing, the CS1024-RSA public key accelerator has been approved for use in a demanding payment application by a leading EU company.

There are two types of security algorithms. Symmetric cryptography is used with ciphers such as AES and relies on a shared key between the two parties. In the case of applications such as payment or on-line banking, the much more complex algorithms required for asymmetric or public key cryptography are required. These algorithms use very large numbers (1024- and 2048- bits) which require specialized engines to meet the demands of high speed transaction processing. This is the value proposition presented by the CS1024.

Furthermore, in these applications, the companies providing the systems must be certified to very high quality standards such as common criteria EAL4 through ISO/IEC 15408. In order for the CS1024 to be used in this class of application, extensive qualification of the engine was required. Between testing conducted by Crack Semiconductor and its customer, the engine was subjected to weeks of continuous operations through billions of 1024-bit operations to confirm that it was fully bug free.

“We are very pleased to have passed the acceptance testing in this demanding payment application,” said Art Low, President and CTO of Crack Semiconductor. “We worked very closely with the customer over the last nine months to deliver the first engine and ensure it was fully compliant to the standards. I am also pleased to report that the customer is so happy with the outcome of this first project that they have now engaged with us to develop a follow-on product with substantially higher performance.”

This initial delivery of the CS1024 is targeted to work with even low cost, medium performance FPGAs such as the Xilinx Spartan-3 or Altera Cyclone products. The engine is able to meet the requirements of the design only due to its advanced architecture which offers performance near the theoretical maximum for the multiplier in a highly compact footprint. The core can also be mapped to ASIC or high-end FPGAs where its performance is significantly improved.

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Al Hawtin

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