2012 IEEE International Interconnect Technology Conference Program Committee Announces Invited Speakers

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Conference agenda is final and available at iitc@his.com

The Program Committed for the 15th Annual IEEE International Interconnect Technology Conference (IITC) and Exhibition is pleased to announce a distinguished line-up of invited speakers who will join the keynote speakers in highlighting technology sessions at IITC 2102, held June 4-6th at the DoubleTree Hotel in San Jose, CA and will be preceded by a day-long Short Course on interconnect technologies on Sunday, June 3rd.

The content-rich 3-day agenda is divided into 14 sessions, including the Plenary and two Poster Sessions, that focus on such growth areas as Fine Grain 3D ICs, Contacts and Local Interconnects, Interconnects for Biological Applications, Networks-on-Chip, and Circuits for High-Speed and Low-Power Signaling.

Featured Keynotes and Invited Speakers
Mike Mayberry, VP and Director of Components Research, Intel Corp. will open the event with a keynote entitled “What Lies Ahead for Devices and Interconnects?” In his talk, Mayberry asks, “How far can we see?” and will look at critical incremental advances required to keep moving forward. He will explain how device and interconnect process and architectures require new thinking, and he will talk about new product opportunities.

Following an award presentation, the day continues with sessions on Materials and Processes, 3D and TSVs, and Back End Memory, in addition to two robust poster sessions. Invited speakers for each topic area include Soo-Hyun Kim, Yeungnam University, who will give a presentation titled Atomic Layer Deposition of Ru Thin Films with Enhanced Nucleations using Various RI (O) Metallorganic Precusors and Molecular O2: Applications to Seed Layer for Cu electropplating and Capacitor Electrode; M. Jürgen Wolf, Fraunhofer, ISM - ASSID, who will talk about 3D TSVs and Interposers;Michael Van Buskirk who will present a talk titled Conductive Bridging RAM (CBRAM): A Scalable, Low Power and High Performance Resistive Memory Technology Platform, and a team from CEA-Leti will address Phase Change Memories Challenges: A Material and Process Perspective.

Billy Dally, VP and Chief Scientist, NVIDIA will lead off day two of the conference with his keynote, It’s about the Power: An Architect’s View of Interconnect, in which he will address how continued scaling is causing chips to become power limited, and as a result power dissipation is becoming more important. From his chip architect’s perspective offers, Daly will explain why it is important to optimize the entire interconnect system together, rather than each part in isolation.

Following this keynote, the day’s agenda continues with sessions on Novel Systems and Packaging, Reliability and Characterization, and a second session on Materials and Processes. Invited speakers include presenters from National Chiao Tung University, and the Industrial Technology Research Institute (ITRI) who will present a paper titled, Electrical Performances and Quality Investigations of Integrated Bonded Structures and TSVs for 3D Interconnects; Daniel C. Edelstein, IBM, T.J. Watson Research Center who will address Engineering the Extendibility of Cu/Low-k BEOL Technology; and representatives of GlobalFoundries, Infineon, and FhG CNT will present How to Address Metallization and Reliability Challenges in Today and Tomorrows Technology Nodes.

The final day will begin with a second session on 3D and TSVs, kicked-off by invited speaker,
Subramanian S. Iyer, of IBM Systems and Technology Group, who will present his talk, Scaling in the Third Dimension - Prospects for Silicon-based Interposer and 3D Integration. This will be followed by sessions on Integration, a second session on Reliability and Characterization, concluding with Novel Materials and Systems. Invited speakers for this day include Bill Taylor from GlobalFoundries, who will present a paper, BEOL Challenges for 14nm Node and Beyond; and Keren Bergman, from Columbia University, who will talk about Nanophotonic Interconnection Networks for Performance-Energy Optimized Computing.

Conference Logistics
The detailed Technical Program including the poster sessions is now available for download at http://www.his.com/~iitc/techprogram.html. Registration for the event is now open at http://www.his.com/~iitc/reginfo.html. The last day to register at the early registration fee is Monday, May 14. The last day to register on-line at regular pricing is Friday, May 25. After May 25, you may register at the conference at the regular pricing.

Exhibitors and Sponsors
The sponsorship committed for IITC 2012 reports an approximate attendance of 400 researchers, technologists and suppliers and would like to offer exhibitors and sponsors a unique opportunity to reach their target audience of engineers, scientists, customers and suppliers community by sponsoring the 2012 conference. The committee is pursuing industrial sponsorships both as a means to help defray the registration costs to the conference attendees as well as to provide sponsors with ideally targeted, high visibility advertising. IITC 2012 will offer a number of options to potential sponsors that include exhibition space and seminar rooms. For details on Exhibiting and Sponsorship, please visit http://www.his.com/~iitc/exhibitor.html.

About the IEEE IITC Conference and Exhibition
The IEEE IITC Conference and Exhibition attracts professionals from industry, academia, and national laboratories in semiconductor processing, interconnect design, and equipment development. Conference topics include both fundamental and applied research, as well as issues related to introduction into manufacturing. The U.S. venue is one of three locations for this premier technology conference, which rotates annually between the U.S., Europe and Asia. For further details about supplier seminar opportunities or other aspects of the conference, please contact iitc@his.com.

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Ruth Brain, IITC Publicity Chair
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