Arasan Chip Systems Announces MIPI® compliant Low Latency Interface (LLI) IP solution

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Arasan’s contribution to both the MIPI LLI v1.0 and M-PHY specifications underpins these configurable and compatible IP’s that deliver on the promise of LLI.

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We have invested extensively to co-architect and co-develop the LLI controller and the M-PHY to be rapidly configured and deployed to the myriad of SoC and interconnect architectures in the customer base.

Arasan Chip Systems, Inc. (“Arasan”), a leading provider of Total IP Solutions, announced today the availability of their MIPI LLI controller IP along with a matching Type 1 M-PHY, the latest additions to its prominent MIPI portfolio.

Both the Applications Processor and the Baseband Processor for mobile platforms are complex SOC’s. Although the two chips are often integrated into one SoC by a number of chip vendors, a number of high end mobile chipsets are still split into two separate processors. They each have their own system level memory to allow efficient cache refills. LLI is a chip-to-chip link layer interconnect protocol that allows efficient , low-latency cache refills from the DRAM associated with a companion chip, thereby removing the need for two separate sets of DRAM’s and substantially reducing the cost of mobile platforms. LLI requires M-PHY Type 1 as the physical layer.

Arasan has developed a combined LLI controller and M-PHY Type 1 solution, which can be configured for a variety of host buses (like AHB, AXI and OCP), and bandwidth/latency requirements across multiple traffic classes. Using up to six lanes of M-PHY’s this solution offers up to 17 Gbps bandwidth in each direction, with only one clock domain crossing in the LLI controller. Customers are given a choice of either source synchronous or independent clocking in the M-PHY’s for clock and data recovery mechanisms in the analog receivers. Arasan will hold a webinar on May 16, 2012 to disclose further information on this solution. Attendees can register at arasan.com/webinars.

“We have invested extensively to co-architect and co-develop the LLI controller and the M-PHY to be rapidly configured and deployed to the myriad of SoC and interconnect architectures in the customer base”, said Ajay Jain, Director of Product Marketing at Arasan. “Bandwidth, latency, test compliance, power, area, QoS and compatibility are issues that had to be addressed at a holistic level across the two IP’s before they can be effectively leveraged at the broader system level.”

Arasan is ready to engage with customers starting at an architectural consulting level, all the way through the delivery of a properly configured LLI controller RTL and M-PHY macro. As with all other Arasan IP’s, these are delivered with accompanying Verification IP and several other scripts and files required for successful integration into each companion chip.

Availability

Arasan’s MIPI LLI Controller IP Core is available immediately for licensing, including Verilog HDL of the IP Core, Verification IP, synthesis scripts, and documentation. The corresponding M-PHY IP is available as a hard macro targeted to any process node, along with all the customer required support files and documentation.

About Arasan    

Arasan Chip Systems is a leading provider of Total IP Solutions for mobile storage and connectivity applications. Arasan’s high-quality, silicon-proven, Total IP Solutions include digital IP cores, analog PHY interfaces, verification IP, hardware verification kits, protocol analyzers, software stacks and drivers, and optional customization services for MIPI, USB, SD, SDIO, MMC/eMMC, CF, UFS, xD and many other popular standards. Arasan’s Total IP products serve system architects and chip design teams in mobile, gaming and desktop computing systems that require silicon-proven, validated IP, delivered with the ability to integrate and verify both digital, analog and software components in the shortest possible time with the lowest risk.

Unlike many other IP providers, Arasan’s Total IP Solution encompasses all aspects of IP development and integration, including analog and digital cores, hardware development kits, protocol analyzers, validation IP and software stacks and drivers and optional architecture consulting and customization services. Based in San Jose, CA, USA, Arasan Chip Systems has a 16 year track record of IP and IP standards development leadership.

About MIPI Alliance

MIPI Alliance is a global, collaborative organization comprised of companies that span the mobile ecosystem and are committed to defining and promoting interface specifications for mobile devices. MIPI Specifications establish standards for hardware and software interfaces which drive new technology and enable faster deployment of new features and services. For more information, visit http://www.mipi.org .

MIPI® is a registered mark of MIPI Alliance, Inc.

For further information please contact:

Sales Contact:                                                                         
Ron Mabry                                                                             
Arasan Chip Systems, Inc.                                                     
408-282-1600 x108                                                                 
sales (at) arasan (dot) com                                                                 

PR Contact:
Ursula Hultqvist
Arasan Chip Systems, Inc.
408-282-1600 x111
pr (at) arasan (dot) com

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Ursula Hultqvist
Arasan
408-282-1600 x111
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