Absolute Analysis Releases New Enhancements to Investigator for Serial RapidIO

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Multi-lane support has been released, along with an innovative array of connection options.

Absolute Analysis today announced new enhancements to its Investigator for Serial RapidIO (sRIO) solution. The solution now supports multi-lane designs (2x and 4x) with speeds of 1.25, 2.50, and 3.125 Gbps. Faster speeds scheduled for release later this year. These features add to the already existing 1x lane support up to a maximum 6.125 Gbps.

Investigator for Serial RapidIO solves the problem of the lengthy time to debug interoperability problems within a sRIO environment. It contains an advanced feature set that allows engineers to find problems quickly. The user can pre-capture filtering of idle events, clock compensation and Status/NOP Control Symbols to optimize use of the 2GB of event buffer. There is a comprehensive trigger and filtering function available for all sRIO events using a simple drag and drop operation. The user can see and decode high level exchanges between devices or do low level analysis of scrambling and idle sequences. All of this can be done while monitoring multiple links simultaneously, with full time correlation.

Investigator eliminates the need for multiple pieces of test equipment to validate the links. The functions of a traffic generator, protocol analyzer, and BER tester for multiple ports are all fully integrated in to a single box. This not only saves on costs, but also increases space available on the workbench testing area.

One of the unique features that distinguish the Investigator product line is its ability to define and trigger on vendor custom packets and control symbols. This is achieved through its proprietary “protocol database” architecture, which essentially allows users to customize the protocol decodes and define any customizations on the protocol developed by the engineering team.

“Multi-lane protocols such as Serial RapidIO offer both terrific advantages for embedded computing as well as headaches in debugging them,” says Manoj Samanta, VP of Engineering at Absolute Analysis. “Investigator for Serial RapidIO helps relieve the debug effort significantly by capturing complex 4 lane conversations and presenting them in way where engineers can find problems quickly.”

To help facilitate connection to devices under test for multi-lane designs, an array of innovative connectivity options also have been released. Investigator uses a native QSFP connector, and provides options to connect this to CX4, SMA, SFP or mid-bus probe connectors. All are designed to tap into the signal with minimal disturbance.

Availability
Investigator for Serial RapidIO is available now. Lead time for orders is 4 to 6 weeks. For more information on Investigator for Serial RapidIO, visit the product page: http://www.absoluteanalysis.com/solutions/by-protocol/serial-rapid-io.html

About Absolute Analysis
Absolute Analysis develops test equipment that performs complete high speed serial bus verification and validation across standard protocols, custom or proprietary protocols, and mixed protocol environments. Protocol support includes Serial RapidIO, PCI Express, CPRI, OBSAI, Fibre Channel, Ethernet up to 10 Gbps, and many others. Their product lines allow engineers to perform a variety of protocol level tests, including protocol analysis, traffic generation, BER testing, error injection, and impairment testing. All verification is accomplished via a single piece of hardware, and a single user interface, saving customers both time and money.

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Peter Brownell
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