San Jose, CA (PRWEB) May 22, 2012
Correcting errors earlier in the process is, of course, a cost-saving effort in the long run. Sigasi’s type time compiler notifies the designer of certain common errors as the code is typed, however this type-time error checker does not catch all errors. The new integration with Riviera-PRO delivers a new line of defence against bugs and flags all violations of the VHDL language in the code – enabling users to continue to leverage VHDL while delivering access to alternative debugging features.
“Those errors would never make it to tape-out,” says Sigasi’s CEO Philippe Faes. “But they would take up precious time from design engineers and verification engineers.” The integration shortens the feedback cycle between man and machine (or between engineer and compiler). As a result, illegal RTL code will never survive longer than a few minutes, and will only take seconds to correct.
Interested hardware designers are invited to visit Sigasi’s website for a demonstration video: http://www.sigasi.com/aldec-sigasi-integration
Sigasi is a privately held, Angel backed EDA company, making VHDL design easier, more efficient and fun. The Sigasi Pro Platform is used by leading companies in the fields of healthcare, consumer electronics, industrial automation, telecom, aerospace and defense. http://www.sigasi.com
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. http://www.aldec.com