The validation of this mode of operation between different vendors shows the maturity of this approach to the industry.
(PRWEB) October 22, 2013
SoC-e, in collaboration with six other companies (Flexibilis, Hirschmann, Fraunhofer, Kyland, Ruggedcom and Meinberg) took part in the HSR/PRP/PTP Interoperability Testing event that was organized in Lemgo, Germany, on September 22 – 24 as a part of ISPCS 2013. For the first time, the HSR and PRP Networks were tested in combination with IEEE 1588 (PTP) at this Plugfest.
Different IEEE 1588 modes of operation were tested in order to detect interoperability issues and to test device and system compatibility. SoC-e took part in this event with its HSR/PRP switch IP core integrated on three equipment: on a Xilinx Zynq All Programmable SoC HSR/PRP system, on a CPU-less Xilinx Spartan-6 based RedBox and on a General Electric IED. SoC-e validated its IEEE1588 Transparent Clock operation for HSR with a variety of different companies’ equipment, and achieved correction times lower than 10ns.
“The combination of synchronization and redundant networks is a great challenge. HSR rings combined with IEEE 1588 ensure high level of accuracy and reliability. The validation of this mode of operation between different vendors shows the maturity of this approach to the industry,” says Armando Astarloa, Founding Partner of SoC-e.
SoC-e technology is present in different HSR/PRP and 1588 Plugfests worldwide in order to validate and enhance its portfolio of IP cores for communications on critical systems. These activities, in combination with the R&D projects carried out by SoC-e, like the new interoperability laboratory (High Availability Networks laboratory) provide a great added value for its customers.
SoC-e provides the world’s lowest HSR/PRP switching latency time for FPGAs and Programmable SoC’s, enabling HSR rings to support up to 40 nodes. The switching time is independent of frame size, so the latency is not only very short, but it is also very predictable. Such high performance is made possible by a completely hardware-centric architecture that does not require the use of a CPU, making it not only fast and predictable, but also compact and very low power.