Hardent Widens Training Scope by Offering SystemVerilog, OVM, UVM and Functional Hardware Verification Training Through Partnership with Williamette HDL

Extending the training curriculum to include functional verification courses, enables engineers to learn how to ensure that their logic design conforms to specification by using SystemVerilog and Universal Verification Methodology (UVM)

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Hardent offers functional hardware verification training courses including SystemVerilog for Verification, OVM to UVM Transition, Open Verification Methodology (OVM) and Advanced Universal Verification Methodology (UVM)

Hardent Functional Hardware Verification Training Courses

With the practical experience of the instructors, verification engineers will learn to effectively master best-practice usage of the SystemVerilog features and UVM verification.

Montreal (QC) and Beaverton (OR) (PRWEB) May 16, 2013

Hardent Inc., a highly experienced electronic design training academy and a Xilinx Authorized Training Provider, announces its collaboration with Williamette HDL (WHDL) to deliver a new line of training courses in functional hardware verification.

Functional verification has become a critical component of electronic development in achieving a better time-to-market and cost efficiencies. The increases in the complexity and size of today’s System on Chips (SoCs) have intensified the challenges of hardware verification. “Engineers are expected to deliver products with sophisticated functionalities, shorter delivery time and remarkable quality” says Mike Baird, President and Founder of Willamette HDL. “With the practical experience of the instructors, verification engineers will learn to effectively master best-practice usage of the SystemVerilog features and UVM verification.”

Over the last year, Hardent has received an increased demand for functional hardware verification courses. With the addition of the new training courses, Hardent addresses the need of verification engineers. “Our goal is to provide a complete training basket” says Simon Robin, founder and President of Hardent, Inc. “Using the WHDL training material was a natural choice for Hardent as it has become the industry standard for teaching languages and advanced modeling for optimal simulation and synthesis results. This alliance complements our well-established training relationship with Xilinx and we are open to exploring potential engagement with other partners.”

In addition to Xilinx’s Verification with SystemVerilog training, Hardent introduces additional functional verification courses created by WHDL, resulting in over 10 courses on the subject of functional verification. Some of those course subjects are: SystemVerilog for Verification, OVM to UVM Transition, Open Verification Methodology (OVM) and Advanced Universal Verification Methodology (UVM). The classes run from one to four days and range from introductory to advanced level.

For more information about SystemVerilog, OVM, UVM and functional verification training, visit Hardent’s Website to register and secure your space today.

About Hardent
Hardent is a professional services firm providing training, engineering and management consulting to leading worldwide electronics equipment and component manufacturers. Hardent’s experts cultivate innovation in electronics, especially with ASICs, FPGAs, DSPs, embedded software and system design. Hardent consultants are trusted advisers in developing high-complexity products, improving engineering processes, enhancing the team's skills and accelerating products’ time-to-market.

About Williamette HDL
Willamette HDL delivers services and products to help language-based hardware design projects be more successful. Founded in 1993, WHDL has an extensive offering of technology training for SystemVerilog, SystemC, Verilog and VHDL. The company specializes in System Level Verification, which is central to training classes available from WHDL. For more information, go to http://www.whdl.com


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Attachments

Open Verification Methodology (OVM) training as part of Hardent functional hardware verification training Open Verification Methodology (OVM) training course

as part of the functional hardware verification training.


Advanced Open Verification Methodology (OVM) training as part of the functional hardware verification training courses Advanced Open Verification Methodology (OVM) training course

as part of the functional hardware verification training courses.


OVM to UVM transition training as part of Hardent's functional hardware verification training courses OVM to UVM transition training course

as part of the functional hardware verification training courses


Universal Verification Methodology (UVM) training as part of Hardent's functional hardware verification training courses. Universal Verification Methodology (UVM) training course

as part of the functional hardware verification training courses.


Advanced Universal Verification Methodology (UVM) training as part of Hardent's functional hardware verification training courses. Advanced Universal Verification Methodology (UVM) training course

as part of the functional hardware verification training courses.


Verilog Fundamentals for SystemVerilog training course as part of Hardent's functional hardware verification training courses. Verilog Fundamentals for SystemVerilog training course

as part of the functional hardware verification training courses.


SystemVerilog for Verification training course as part of Hardent's functional hardware verification training courses. SystemVerilog for Verification training course

as part of the functional hardware verification training courses.