CORRECTING and REPLACING Altera Announces Industry's First 40-nm FPGAs and HardCopy ASICs : Stratix IV FPGAs and HardCopy IV ASICs Both Offer Transceiver Options

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In the Altera boilerplate, last sentence should read RapidIO is a registered trademark of the RapidIO Trade Association (sted RapidIO is a registered trademark of Mentor Graphics Corporation).

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Today's announcement significantly widens the density, performance and low-power advantages of the Stratix series versus competing offerings

The corrected release reads:


Stratix IV FPGAs and HardCopy IV ASICs Both Offer Transceiver Options

Enabling designers to achieve new levels of integration and innovation, Altera Corporation (NASDAQ:ALTR) today announced the industry's first 40-nm FPGAs and HardCopy® ASICs. The Stratix® IV FPGAs and HardCopy IV ASICs, both with transceivers options, provide unprecedented densities, performance and low-power leadership. The Stratix IV family has up to 680K logic elements (LEs), 2X bigger than Altera's Stratix III family, currently the largest FPGAs on the market. The HardCopy IV ASIC family offers equivalent densities as the Stratix IV devices and features up to 13.3 million gates. Altera® 40-nm devices meet the diverse high-end application needs in a large number of markets such as wireless and wireline communications, military, broadcast and ASIC prototyping.

With the increasing demand for services such as video over Internet, high-speed wireless data and digital TV, designers need to deliver solutions that provide higher data rates, higher interface bandwidths, and increased data processing all in a power-efficient manner. To address these design challenges, Altera is leveraging its innovations in transceivers, memory interfaces, low-power technology and FPGA core architecture to offer new capabilities with its 40-nm devices.

Manufactured on TSMC's 40-nm process, the Stratix IV FPGA family is comprised of two variants, an enhanced variant rich with memory and digital signal processing (DSP) resources (Stratix IV E FPGAs) and an enhanced variant with transceivers (Stratix IV GX FPGAs). Stratix IV GX FPGAs offer up to 48 transceivers operating at up to 8.5 Gbps, which provides designers with the industry's highest available bandwidth, more than twice the bandwidth of any other FPGA. Stratix IV GX FPGAs also feature hard intellectual property (IP) support for PCI Express (PCIe) Gen 1 and 2 and also supports a wide range of protocols including, Serial RapidIO®, XAUI (including DDR XAUI), CPRI (including 6G CPRI), CEI 6G, Interlaken and Ethernet.

To address the low-power demands of customers, the Stratix IV family members feature Altera's patented Programmable Power Technology. This power-saving technology optimizes logic, DSP and memory blocks to maximize performance where needed while delivering the lowest power elsewhere in the design.

For the first time, Altera offers a transceiver-based ASIC option with the new HardCopy IV ASIC family. Using the Stratix FPGAs in design delivers the benefits of FPGA hardware and software co-design and co-verification—saving months in time to market—and the use of HardCopy ASICs delivers the benefits of ASICs in production.

"Today's announcement significantly widens the density, performance and low-power advantages of the Stratix series versus competing offerings," said John Daane, president, CEO and chairman of Altera Corporation. "Combined with the HardCopy ASIC family, Altera is the only company that can offer a complete high-performance solution that allows designers to quickly move from concept to volume production."

The company also announced today enhancements to its Quartus® II design software (See related announcement: "Altera's Quartus II Software Version 8.0 Delivers Unprecedented Performance and Productivity for High-End FPGAs") and delivered IP solutions optimized for 40-nm products. Quartus II software v.8.0 enables designers to achieve efficient team design and fast time to market through the highest performance, logic utilization and lowest compile times in the industry.

Customer and Partner Support

Many of Altera's customers and partners are recognizing the benefits of Altera's Stratix IV and HardCopy IV ASICs. To see what representatives of these companies are saying, visit:


Customers can start their Stratix IV designs using Altera's Quartus II design software v.8.0. Engineering samples of the first member of the Stratix IV device family will be available in the fourth quarter of 2008. Customer tapeouts for HardCopy IV ASICs will start in the third quarter of 2009. For more information about Stratix IV devices, visit For information on HardCopy IV ASIC devices, visit

About Altera

Altera programmable solutions enable system and semiconductor companies to rapidly and cost effectively innovate, differentiate and win in their markets. Find out more at

Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations and all other words that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. RapidIO is a registered trademark of the RapidIO Trade Association.

Safe Harbor

This contains "forward-looking statements" that are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Forward-looking statements are generally preceded by words that imply a future state or that imply that a particular future event or events will occur such as "will." Investors are cautioned that all forward-looking statements involve risks and uncertainty, including without limitation the risk that future performance is dependent on product development schedules, the design performance of software and other tools, as well as the company's and third parties' development technology and manufacture capabilities. Please refer to the company's Securities and Exchange Commission filings, copies of which are available from the company without charge.


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