Blue Pearl Software Names Kavita Snyder VP of Worldwide Applications

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New position addresses growing worldwide demand for EDA software that addresses the needs of advanced FPGA designers

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Blue Pearl Software, Inc, a leading provider of EDA software for the FPGA ecosystem, announced that it has appointed Kavita Snyder as Vice President of Worldwide Applications. Ms. Snyder will report to Paul Wilhelmsen, Vice President of Sales, and she will manage the worldwide applications team for the company’s electronic design automation (EDA) software.

Blue Pearl Software Suite, for Windows and Linux operating systems, accelerates FPGA implementation with comprehensive RTL analysis, clock-domain crossing (CDC) checks, and automatic Synopsys Design Constraints (SDC) generation for FPGA, ASIC and SOC designs. Its visualization and validation technology gives users immediate feedback for validating automatically generated pre-synthesis longest paths and timing constraints.

“Kavita has a successful track record managing and growing application teams for leading edge technology companies” stated Ellis Smith, CEO of Blue Pearl Software. “We look forward to building a world class applications team to address the growing demand for our design analysis, clock domain crossing checking and timing constraint generation tools for FPGA and ASIC designs.”

Ms. Snyder has over 25 years in applications and operations roles with software and semiconductor companies. Prior to Blue Pearl, she worked at several technology companies, including Magma Design Automation, Jasper Design Automation, Atrenta, Synopsys, Synplicity and Mitsubishi. She holds a BS in Computer Engineering from San Jose State University.

Earlier this year, Blue Pearl Software announced Release 6.0 of its Blue Pearl Software Suite with capabilities that support FPGA designers, and support Xilinx’s VivadoTM flow. FPGA designers can learn more by visiting and signing up for a hands-on workshops or software evaluation.

About Blue Pearl Software
Blue Pearl Software Suite accelerates FPGA implementation with comprehensive RTL analysis, CDC checks and automatic SDC generation. Its Visualization Verification Environment ™ and design technology give users immediate feedback for validating automatically generated pre-synthesis longest paths and SDCs. They are subsequently used to drive the efficiency of synthesis and place & route tools. The software runs natively on Windows and Linux platforms, and is used for FPGA, ASIC and SOC design.
For the latest news and information on Blue Pearl Software, visit

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Shakeel Jeeawoody