IP Cores, Inc. Announces Shipments of the FPGA Version of Its 100 Gbps MACsec IP Cores

IP Cores, Inc. (http://www.ipcores.com) announces shipments of an FPGA Version of the 100 Gbps MACsec (IEEE 802.1AE) encryption/decryption core.

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Palo Alto, California (PRWEB) February 04, 2014

IP Cores, Inc., California, USA (http://www.ipcores.com) has announced shipments of an FPGA version of its MSP10 core that supports line-speed MACsec encryption and decryption for the 100 Gbps Ethernet solutions.

“An FPGA version of our successful MSP10 MACsec core extends our portfolio of high-speed encryption cores,” said Dmitri Varsanofiev, CTO of IP Cores, Inc. “The core is fully integrated with secure association context lookup and MACsec header parsing, insertion, and removal. Glueless interface to most popular 100G Ethernet MAC solutions lead to a straightforward integration”.

MSP10 100 Gbps Ethernet Encryption Core

MSP10 MACsec IP core delivers full 100 Gbps data rate on any frame mix, including the shortest 64-byte Ethernet frames. Variety of the core configurations permits up to tens of thousands of concurrently active secure associations. All features of the MACsec standard are supported, including the recent extensions: IEEE 802.1AEbw (XPN, 64-bit extended packet numbering) and IEEE 801.1AEbn (GCM-AES-256 encryption).

MSP10 core has been made available for all modern FPGA families, including those manufactured by Altera and Xilinx, in addition to the original ASIC targeting.

MACsec

MACsec is the IEEE MAC Security standard (also known as 802.1AE) that defines connectionless data confidentiality and integrity for media access protocols. It is standardized by the IEEE 802.1 working group. MACsec specifies the implementation of a MAC Security Entities (SecY) and defines MACsec frame format, which is similar to the Ethernet frame, but includes additional fields (Security Tag and Message authentication code or ICV).

MACsec uses Galois/Counter Mode of Advanced Encryption Standard cipher with 128-bit key (AES-GCM-128) as a default cipher suite.

Security tag inside each frame in addition to Ethertype includes association number within the channel and packet number to provide unique initialization vector for encryption and authentication algorithms as well as protection against replay attack as well as the secure channel identifier.

About IP Cores, Inc.

IP Cores is a rapidly growing California company in the field of security, error correction, and DSP IP cores. Founded in 2004, the company provides hardware IP cores for communications and storage fields, including AES-based ECB/CBC/OCB/CFB, AES-GCM and AES-XTS cores, MACsec 802.1AE, IPsec and SSL/TLS protocol processors, flow-through AES/CCM cores with header parsing for IEEE 802.11 (WiFi), 802.16e (WiMAX), 802.15.3 (MBOA), 802.15.4 (Zigbee), public-key accelerators for RSA and elliptic curve cryptography (ECC), true random number generators (TRNG), cryptographically secure pseudo-random number generators (CS PRNG), secure SHA and MD5 cryptographic hashes, lossless data compression cores, low-latency fixed and floating-point FFT and IFFT cores, as well as cyclic, Reed-Solomon, LDPC, BCH and Viterbi forward error correction (FEC) decoder cores.

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