IP Cores, Inc. Ships a Multichannel AES/DES Encryption IP Core Targeting the Cable Headend Designs

IP Cores, Inc. (http://www.ipcores.com) announces shipment of a multichannel AES/DES encryption core intended for cable headend design.

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Palo Alto, CA (PRWEB) August 19, 2014

IP Cores, Inc., California, USA (http://www.ipcores.com) has announced shipments of a multichannel AES/DES encryption core that can be used in high-speed headend designs for cable standards, including DOCSIS 3.0.

“DCS3 is a generic multichannel AES/DES encryption core,” said Dmitri Varsanofiev, CTO of IP Cores, Inc. “It can be useful in a design that requires AES and DES encryption of high-throughput data stream running at 10-100 Gbps yet comprised of multiple independent channels utilizing non-scalable encryption modes like CBC. This design challenge is typical for the cable headend designs, including DOCSIS 3.0”.

DCS3 AES/DES Encryption Core

DCS3 IP core delivers scalable throughput for AES and DES encryption in the “feedback” modes (including CBC). Channelized architecture of the core fits well into multiple communication designs, including the headend equipment for cable networks like DOCSIS 3.0.

About IP Cores, Inc.

IP Cores is a rapidly growing California company in the field of security, error correction, and DSP IP cores. Founded in 2004, the company provides hardware IP cores for communications and storage fields. Its portfolio includes AES-based ECB/CBC/OCB/CFB, AES-GCM and AES-XTS cores, MACsec 802.1AE, IPsec and SSL/TLS protocol processors, flow-through AES/CCM cores with header parsing for IEEE 802.11 (WiFi), 802.16e (WiMAX), 802.15.3 (MBOA), 802.15.4 (Zigbee), public-key accelerators for RSA and elliptic curve cryptography (ECC), true random number generators (TRNG), cryptographically secure pseudo-random number generators (CS PRNG), secure SHA and MD5 cryptographic hashes, lossless data compression cores, low-latency fixed and floating-point FFT and IFFT cores, as well as cyclic, Reed-Solomon, LDPC, BCH and Viterbi forward error correction (FEC) decoder cores.

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