Arteris Delivers FlexNoC Physical™ Interconnect IP to Accelerate SoC Layout

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Physically-aware IP leverages on-chip interconnect architecture for automated timing closure, first-pass place & route success

“We are helping customers cut down place and route cycles by providing their layout teams better starting-point data.”said K. Charles Janac, President and CEO of Arteris.

Arteris Inc., the inventor and only supplier of silicon-proven commercial network-on-chip (NoC) interconnect IP solutions, today announced availability of Arteris FlexNoC Physical interconnect IP, a breakthrough that accelerates system-on-chip (SoC) physical design.

Arteris FlexNoC interconnect IP has always been layout friendly because the Arteris NoC technology uses fewer wires, enables fine-grained pipeline register placement nearly anywhere in the interconnect, and allows distributed IP placement. This technology has been providing the world’s top semiconductor design teams the benefits of minimizing wire routing congestion and reducing silicon area, cost and power consumption for many years.

FlexNoC Physical interconnect IP further enhances layout quality-of-results (QoR) and productivity by importing user-defined and production floorplans, automatically configuring pipelines to meet timing closure constraints, and separating the FlexNoC interconnect IP instances at a physical level so they can be routed separately from the rest of the SoC.

The benefits of FlexNoC Physical IP include:

  •     Reduces or eliminates excessive P&R iterations – To resolve timing closure errors on long paths, SoC designers often have to iterate over multiple P&R runs, which can be very expensive. Optimizing the NoC interconnect IP early, prior to full SoC P&R, reduces the likelihood of timing closure issues during layout.
  •     Eliminates trial-and-error timing closure with automated pipeline configuration – By analyzing the actual interconnect IP in the front-end design phase and automatically configuring pipeline stages as appropriate, chip teams hand over to the backend team a netlist that will close timing by design.
  •     Optimizes Quality-of-Results (QoR) – SoC teams often over-design their chips in the front-end stage to avoid timing problems in the back-end. FlexNoC Physical IP intelligently estimates and predicts in the front-end phase where timing issues will occur in the back-end, allowing design teams to implement the minimum number of pipeline stages to achieve desired frequencies, while minimizing latencies and power consumption.
  •     Separates the FlexNoC interconnect physical IP from the rest of the SoC – FlexNoC Physical offers features to separate the interconnect IP at the physical level the same way that it allows such isolation at the architectural level. Users can now generate interconnect floorplan outlines and treat the interconnect as a separate IP to be independently placed and routed by itself. Such a separation simplifies the job of the layout team.

The FlexNoC Physical solution leverages the architectural knowledge of the SoC interconnect not only to accelerate timing closure but to also improve QoR by using less slack to meet timing, further reducing SoC silicon area and improving performance.

To enable this automation, FlexNoC Physical can import floorplans (in LEF / DEF format) along with process technology information. This layout and process information is used to quickly find an optimum placement of the FlexNoC Physical fabric IP components in the layout, and determines where pipeline stages must be used while minimizing area and latency. In addition to generating a new RTL instance with the added pipeline stages, FlexNoC Physical exports placement information to physically-aware synthesis tools and place and route tools.

“Using FlexNoC Physical delivers two valuable benefits: First, it allows SoC architects to visualize the physical implications of their topologies early in the design cycle, and second, it helps the RTL implementation team to automatically add pipelines for timing closure, cutting months off complex SoC development cycles” said K. Charles Janac, President and CEO of Arteris. “We are helping customers cut down place and route cycles by providing their layout teams better starting-point data.”

The Linley Group, Mike Demler, Senior Analyst
“Arteris is solving an important set of back-end problems with technology that works earlier in the SoC design flow” said Mike Demler, Senior Analyst, at The Linley Group. “FlexNoC Physical IP has the potential to significantly decrease timing issues experienced in the layout stage, reducing P&R iterations and engineering change orders (ECOs) and saving cost and schedule time.”

Synopsys, Bijan Kiani, Vice President of Marketing, Design Group
“Arteris FlexNoC Physical has the promise to improve layout productivity by providing Synopsys tools, such as Design Compiler Graphical and IC Compiler II, with improved timing closure information and more accurate RTL data,” said Bijan Kiani, Vice President of Marketing, Design Group at Synopsys. “We look forward to working with mutual customers to validate these propositions.”

Arteris FlexNoC Physical is available today for early access customers.

About Arteris
Arteris, Inc. provides Network-on-Chip interconnect IP and tools to accelerate System-on-Chip semiconductor (SoC) assembly for a wide range of applications. Rapid semiconductor designer adoption by customers such as Samsung, Altera, and Texas Instruments has resulted in Arteris being the only semiconductor IP company to be ranked in the Inc. 500 and Deloitte Technology Fast 500 lists in 2012 and 2013. Customer results obtained by using the Arteris product line include lower power, higher performance, more efficient design reuse and faster SoC development, leading to lower development and production costs. More information can be found at

Arteris, FlexNoC and the Arteris logo are trademarks of Arteris. All other product or service names are the property of their respective owners.

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Kurt Shuler
Arteris Inc.
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