“Arteris FlexNoC IP has been at the heart of most of the world’s ADAS systems, helping SoC design teams create these extremely complex SoCs while meeting ISO 26262 functional safety requirements,” said K. Charles Janac, President and CEO of Arteris.
Campbell, Calif. (PRWEB) May 31, 2016
Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced that Dream Chip Technologies GmbH has licensed Arteris FlexNoC interconnect IP with the Arteris FlexNoC Resilience Package for use in the European Commission / ENIAC THINGS2DO automotive advanced driver assistance systems (ADAS) reference development platform project.
Arteris FlexNoC interconnect IP is the on-chip communications backbone of most of the world’s application processors, digital baseband modems and ADAS SoCs. The FlexNoC Resilience Package adds data protection features required to obtain higher ISO 26262 automotive safety integrity levels (ASIL) by implementing on-chip error code correction (ECC) protection, hardware duplication and redundancy, unit checking, data monitoring and built in self-test (BIST).
Dream Chip Technologies (DCT) has designed a large number of very complex systems-on-chip (SoC) for many customers worldwide and was selected as the design service lead for the ADAS MPSoC European THINGS2DO project. The objective of the project is to create a camera-based ADAS reference platform that benefits automotive Tier 1companies through not only advanced technology but also by shortening the time-to-market and design cycles for innovative automotive electronics. Two tape outs are scheduled, one in early 2017 and another in early 2018, both using the 22nm FDSOI semiconductor process at Global Foundries in Dresden/Germany.
“The competing goals of creating a highly complex ADAS SoC with functional safety requirements while reducing Tier-1 TTM motivated us to choose Arteris FlexNoC over other interconnects,” said Dr.-Ing. Jens Benndorf, managing director and COO of Dream Chip Technologies. “The Arteris NoC technology reduces wire routing congestion and QoS issues while allowing us to more easily implement the data protection features required for ADAS systems to meet higher levels of ISO 26262 ASIL certification.”
“Arteris FlexNoC IP has been at the heart of most of the world’s ADAS systems, helping SoC design teams create these extremely complex SoCs while meeting ISO 26262 functional safety requirements,” said K. Charles Janac, President and CEO of Arteris. “We are excited that Dream Chip Technologies has chosen our technology as the communications foundation for this reference platform, which has the promise to enable new autonomous vehicle capabilities for European Tier-1 automotive suppliers.”
About Dream Chip Technologies
Dream Chip Technologies GmbH (DCT) is the largest independent German Design Service company specialized in the development of large ASICs, FPGAs, embedded software and systems with a strong application focus on automotive vision systems (ADAS). Companies from different industrial sectors worldwide rely on DCT's expertise and outstanding engineering skills. It is DCT’s mission to bridge the gap between demand and offer by supporting their customers by sophisticated vision technologies, thus enabling them to launch new products without neglecting its core business. This strategy ensures business stability and steady growth through product innovations simultaneously. DCT's headquarters are located in Northern Germany near Hanover. For more information, please visit the company’s web site at: http://www.dreamchip.de
Arteris, Inc. provides system-on-chip (SoC) interconnect IP and tools to accelerate SoC semiconductor assembly for a wide range of applications. Rapid semiconductor designer adoption by customers such as Samsung, Huawei / HiSilicon, Mobileye, Altera, and Texas Instruments has resulted in Arteris being the only semiconductor IP company to be ranked in the Inc. 500 and Deloitte Technology Fast 500 lists in 2012 and 2013. Customer results obtained by using the Arteris product line include lower power, higher performance, more efficient design reuse and faster SoC development, leading to lower development and production costs. More information can be found at http://www.arteris.com.
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