Blue Pearl Software Collaborates with Microsemi to Accelerate FPGA Verification for Mil/Aero Designs

Share Article

Visual Verification Suite 2017.1 Adds Built-in Support for Microsemi Radiation Tolerant Libraries and Extended Formal Analysis

News Image

Blue Pearl Software, Inc., a leading provider of design automation software for ASIC, FPGA and IP RTL verification, today announced Visual Verification Suite 2017.1. The release extends its leadership in RTL verification for FPGAs with new support for Microsemi® Corporation FPGAs including radiation-tolerant FPGAs used widely in military and aerospace applications along with extended Formal RTL analysis. With Visual Verification Suite 2017.1 users now have access to built-in libraries for Intel®/Altera, Microsemi® Corporation and Xilinx® to accelerate setup, analysis and debug of FPGA IP and designs.

“Since 1992 Microsemi FPGAs have achieved flight heritage on many programs with both antifuse and flash-based FPGAs,” said Ken O’Neill, director of marketing, space and aviation at Microsemi. “We introduced the industry’s first flash-based radiation tolerant FPGA with the RT ProASIC3, which provides resistance to radiation-induced configuration upsets in low power space applications. Blue Pearl’s Visual Verification Suite in combination with our Libero Design Suite offers designers a comprehensive easy-to-use RTL verification solution to accelerate development and ensure designs do not have metastability issues caused by clock domain crossing.”

“Our growing military and aerospace customer base has requested built-in support of Microsemi’s FPGAs due to their unique radiation resistance required in space applications, “said John Molyneux, President and COO of Blue Pearl Software. “In addition to support for Microsemi libraries, including RT ProASIC3 and IGLOO FPGAs, the new release extends our formal-verification based analysis, further strengthen the Virtual Verification Suite’s Clock Domain Crossing offering.”

The 2017.1 release also provides updates to the Analyze RTL™ linting and debug, Clock Domain Crossing analysis and Synopsys Design Constraints (SDC) generation to accelerate the RTL verification. Engineered to maximize RTL find/fix rates for both novice and expert users, the Visual Verification Suite 2017.1 uniquely provides easy setup, support for ASICs and FPGAs, consistent results, a DO-254 verification package, and runs on both Linux and Windows.

To Learn More
For more information on how you can accelerate your RTL verification with Visual Verification Suite, talk to a local sales representative or visit http://www.bluepearlsoftware.com to watch feature videos and read our white papers. Download the latest release at http://www.bluepearlsoftware.com/downloads.

About Blue Pearl Software
Blue Pearl Software, Inc. is a provider of DO-254 compatible design automation software for ASIC, FPGA and IP RTL verification. Our customers are RTL managers and developers, in military, aerospace, semiconductor, medical, communications and safety critical design companies, who wish to avoid costly and time consuming design spins due to simulation / HW mismatches, invalid constraints and clocking issues. The Visual Verification Suite is designed, tested and supported in the United States of America.

Press Contact:
Jenn Treiber, Blue Pearl Software, +1- 408.961.0121, x341
jenn.treiber(at)bluepearlsoftware(dot)com

Share article on social media or email:

View article via:

Pdf Print

Contact Author

Jenn Treiber
Blue Pearl Software
408-961-0121 Ext: 341
Email >
Follow us on
Visit website