Opal Kelly Introduces SYZYGY - An Open Standard for FPGA System Peripheral Connectivity

Share Article

Filling the gap between existing PMOD and FMC standards, SYZYGY focuses on an economical interface for high-performance single-purpose peripherals such as data acquisition and machine vision devices.

Opal Kelly SYZYGY Hub

Opal Kelly SYZYGY Hub

We envision SYZYGY occupying the space between present standards where pin economy, low cost, and high performance converge.

Opal Kelly, a leading producer of powerful FPGA modules that provide essential device-to-computer interconnect using USB or PCI Express, announced the release of SYZYGY™, a new open standard for connecting high-performance peripherals to FPGA hardware.

SYZYGY is intended to satisfy the need for a compact, low cost, low pin-count, high-performance connectivity solution between FPGAs and single-purpose hardware peripherals. Devices for high-speed data acquisition, digital image capture, software-defined radio, and digital communication were the primary inspiration for the development of SYZYGY.

The SYZYGY specification defines two connector types: the Standard SYZYGY connector offers up to 28 single-ended, impedance-controlled signals, 16 of which may be defined as differential pairs for interface standards such as LVDS. The Transceiver SYZYGY connector boasts four lanes of Gigabit-class transceiver connections and also offers up to 18 single-ended signals. The Transceiver connector is intended for use with JESD204B data acquisition, SFP+ transceivers, and other devices requiring high-speed SERDES. Both Standard and Transceiver connectors have optional low-cost, high-performance coaxial or twinaxial cable assemblies.

Designed to accommodate the wide range of I/O voltages common with FPGA systems, SYZYGY defines SYZYGY DNA and SmartVIO™. SYZYGY DNA is a simple way for peripherals to communicate personality data such as manufacturer name, product name, and serial number to the carrier. SmartVIO is included in the DNA payload and defines the range of I/O voltages acceptable to the peripheral so that carriers can set I/O voltages accordingly.

Opal Kelly has offered SYZYGY as an open standard, making it free to license by carrier and peripheral manufacturers. This licensing approach is to encourage consistency, proliferation, and a healthy ecosystem where carrier and peripheral manufacturers, semiconductor device manufacturers, educational institutions, and research organizations are invited to develop their own additions.

"SYZYGY is intended to fit the sweet spot of peripheral connectivity between the existing low-performance, low pin-count PMOD and the expensive, high-performance ultra-high pin-count of FMC," said Jake Janovetz, President of Opal Kelly Incorporated. "We envision SYZYGY occupying the space between present standards where pin economy, low cost, and high performance converge. Carriers could offer multiple connectivity options to provide additional flexibility to system implementers."

In addition to the specification, Opal Kelly will release their upcoming SYZYGY™ Compatible carrier, the Hub, an open-source board incorporating a Xilinx Zynq SoC FPGA. As an open-source hardware design, the Hub will serve as a SYZYGY reference platform for adopters and manufacturers. Opal Kelly also plans to add SYZYGY support to several future FPGA integration products.

About Opal Kelly

Opal Kelly, founded in 2004, offers a range of powerful, off-the-shelf, USB-based FPGA modules, including the easy-to-use Opal Kelly FrontPanel™ software interface and robust API. Opal Kelly products provide the essential device-to-computer interconnect for efficient and fast product prototyping, testing, development, and OEM integration. Development engineers, researchers, teachers and serious hobbyists, worldwide, use Opal Kelly modules for an efficient and economical interconnect solution that shortens development time, fills expertise gaps, and dramatically accelerates time to market. For more information, or to download the SYZYGY Specification, please visit syzygyfpga.io

Share article on social media or email:

View article via:

Pdf Print

Contact Author

Jake Janovetz
Visit website