COLUMBUS, Ohio (PRWEB) May 07, 2018
StreamDSP announces immediate availability of VITA 17.3 sFPDP Gen 3 IP Core.
The recently approved VITA 17.3 specification, also known as Serial Front Panel Data Port (sFPDP) Gen 3, is a next-generation communications protocol designed as the successor to VITA 17.1. VITA 17.3 improves link efficiency and bandwidth by using the same 64B/67B encoding technology found in newer protocols such as Interlaken and Serial RapidIO Gen 3, and also supports multi-lane channel bonding to allow for maximum bandwidth scalability. Like VITA 17.1, VITA 17.3 supports both framed and unframed data types and is designed to easily interface to existing systems. VITA 17.3 is ideal for low-latency remote sensor applications, FPGA chip-to-chip interfaces, FPGA optical interfaces, and backplane interconnect.
The StreamDSP sFPDP Gen 3 IP core is a fully-compliant implementation of the VITA 17.3-2018 standard. To allow for system upgrades, StreamDSP was able to keep the user interface to the sFPDP Gen 3 IP core virtually the same as their current (and very popular) 17.1 IP core.
The StreamDSP sFPDP Gen 3 IP Core currently supports the following FPGA devices:
Xilinx Zynq UltraScale Plus
Xilinx Virtex UltraScale Plus
Support the for the following devices is underway and will be available soon...
Xilinx Kintex UltraScale
Xilinx Virtex UltraScale
In addition to the devices listed above, StreamDSP is committed to adding support for ANY transceiver based FPGA family with a valid request.
StreamDSP provides "ready-to-run" simulations and reference designs targeted to popular development boards for each of the supported FPGA families. Unlike many other vendors, StreamDSP offers free time-limited evaluations with full technical support. This allows StreamDSP's customers to quickly and easily verify proper operation both in simulation and also with their chosen device family to minimize integration time and reduce risk. The wide range of FPGA device support also allows StreamDSP to do extensive compatibility testing between different FPGA families to ensure error-free communications between all FPGA families. The sFPDP Gen 3 IP core from StreamDSP makes it simple for customers to connect Intel/Altera and Xilinx devices together with very high bandwidth connections.
StreamDSP served an important role in defining the VITA 17.3 standard by acting as the VITA 17.3 Working Group Chairperson. "We would like to thank all members of the VITA 17.3 Working Group for the hard work and dedication over the past few years," said Greg Schueller, StreamDSP's Director of Business Development. "The industry has been asking for a next-generation Serial FPDP, and the group was able to design a new specification to satisfy all of the requirements and add some exciting new features. We hope Serial FPDP Gen 3 will allow Serial FPDP to continue filling the needs of high-bandwidth, low-latency remote sensor data connections and flexible system interconnect solutions that are easily scalable", added Greg.
Greg Schueller, Director of Business Development
Tel. +1 (855) DSP-FPGA
Fax. +1 (855) 377-3742
StreamDSP LLC, 20 S Third St, Suite 210, Columbus, OH, 43215, USA
More information about the Serial FPDP VITA 17.3 Standard can be found at http://www.vita.com.
About StreamDSP LLC
StreamDSP is an intellectual property (IP) company specializing in video, serial communications, and data storage solutions for Field Programmable Gate Array (FPGA) devices. Headquartered in Columbus, OH, StreamDSP has over 50 years of combined experience serving the military and commercial markets, and is focused on developing IP and providing custom design services for FPGAs.