Bluespec, Inc. Joins the Xilinx® Partner Program, Offering Drop-in Ready RISC-V Processors for Xilinx FPGAs

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Bluespec, Inc. joins the Xilinx Partner Program and releases two RISC-V processor families, optimized for use on Xilinx FPGAs.

Bluespec, Inc.

Bluespec, Inc.

Bluespec, Inc. releases two processor families tailored to meet different performance and resource utilization requirements. The RISC-V processor cores are optimized, verified, and drop-in ready for use in Xilinx’s Vivado and Vitis design environments.

Bluespec, Inc., a founding member of RISC-V International and supplier of RISC-V processor IP and tools, announced that they have joined the Xilinx Partner Program and have released two RISC-V processor families, optimized for use on Xilinx FPGAs. The Xilinx Partner Program is a worldwide ecosystem of qualified companies that offer acceleration solutions, IP cores, design services, and board development and production. By joining the Xilinx Partner Program and offering easy to use RISC-V processors to the Xilinx community, Bluespec is expanding the RISC-V ecosystem and helping to drive the adoption of the open Instruction Set Architecture.

The two processor families announced by Bluespec are tailored to meet different performance and resource utilization requirements. The RISC-V processor cores are optimized, verified, and drop-in ready for use in Xilinx’s Vivado and Vitis design environments. The two Bluespec RISC-V families are:

RV32 BMR Family     
The BMR family is targeted at applications using a Real-Time Operating System or running on bare metal. The RV32IMAC BMR family is optimized for an efficient and low resource cost implementation. It supports the base Integer instructions (I), Integer Multiplication and Division (M), Atomic (A), and Compressed (C) instructions and features a five-stage pipeline and operates up to 250 MHz.

RV32 SCL Family
The SCL family targets applications that require a single processor core running Linux and is optimized for a mix of high-performance and low resource utilization.

The first two available processors in the SCL family are the RV32IMAC SCL, which supports the base Integer instructions (I), Integer Multiplication and Division (M), Atomic (A), and Compressed (C) instructions. The second is the RV32GC SCL processor that adds Single and Double-Precision Floating-Point instructions (F and D). The RV32 SCL family features a five-stage pipeline and operates up to 200 MHz.

“Joining the Xilinx Partner Program and offering the first RISC-V processors adapted for use on Xilinx FPGAs signals Bluespec’s commitment to bringing the benefits of open-source RISC-V processors to the Xilinx user community by offering pre-verified, optimized, and drop-in-ready RISC-V processors” says Bluespec VP of Product and Business Development, Loren Hobbs. “We believe in the tremendous potential of the RISC-V open Instruction Set Architecture ecosystem and are delivering on this promise by providing packaged RISC-V IP that allows Xilinx users to get up and running with RISC-V in minutes. Xilinx users now have a viable alternative to proprietary processor architectures and a simplified on-ramp for using RISC-V processors in their designs.”

Bluespec Inc will continue to develop and provide tailored RISC-V solutions and will be announcing the availability of additional RISC-V processor implementations including micro footprint RISC-V processors and domain specific RISC-V accelerators in the coming weeks.

For more information, visit https://bluespec.com/.

About Bluespec Inc
Bluespec is driving the adoption of RISC-V processors for use in FPGAs. Working in partnership with FPGA vendors, Bluespec provides optimized and pre-verified RISC-V cores and tools to enable customers to efficiently integrate, program, accelerate and verify RISC-V cores from best-in-class RISC-V open-source projects. We enable companies to take advantage of RISC-V’s cost reduction and freedom to innovate without the support and productization risks of open-source hardware. For more information, visit https://bluespec.com/.

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Loren Hobbs
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