High Reliability FPGA Design Webinar Hosted by Blue Pearl Software

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Blue Pearl Software Inc., a leading provider of design automation software for ASIC, FPGA and IP RTL verification, is partnering with ADIUVO Engineering and Training LTD, to deliver a free webinar titled High Reliability FPGA Design

Adam Taylor, a chartered engineer and fellow of the Institute of Engineering and Technology

Blue Pearl Software Inc., a leading provider of design automation software for ASIC, FPGA and IP RTL verification, is partnering with ADIUVO Engineering and Training LTD, to deliver a free webinar titled High Reliability FPGA Design. The webinar will discuss the challenges faced by embedded system design teams, including governance and design standards. Attendees will learn mitigation techniques to avoid serious FPGA related failures including systematic and random faults.

The webinar will take place October 14,20 (4:30pm UK, 5:30pm CET, 8:30 AM PST) and will be hosted by Adam Taylor, Founder and Principal Consultant at ADIUVO.
The webinar is a must for embedded systems FPGA design teams and managers as it explores design challenges they face and how to mitigate their impact to ensure robust and safe systems.

To be our guest please register at https://app.livestorm.co/adiuvo-engineering/introduction-to-high-reliability-design.

About Adam Taylor

Adam is a chartered engineer and fellow of the Institute of Engineering and Technology. Over his multi-decade career, he has had experience within the public and private sectors, developing FPGA-based solutions for a range of applications including RADAR, nuclear reactors, satellites, cryptography and image processing. Adam is also a Visiting Professor of embedded systems at the University of Lincoln. Education is his deepest passion and he has delivered thousands of hours' worth of training to corporate clients and casual hardware enthusiasts alike. Learn more at https://www.adiuvoengineering.com.

About Blue Pearl Software

Blue Pearl Software, Inc. is a leading provider of DO-254 compatible design automation software for ASIC, FPGA and IP RTL verification. Our customers are RTL managers and developers, in military, aerospace, semiconductor, medical, communications and safety critical design companies. The Visual Verification™ Suite speeds block and project level verification with advanced integrated RTL structural and formal linting, constraint generation and clock domain crossing analysis. Our usability is unmatched in the industry and can help your design team accelerate development and produce high reliability designs. The Visual Verification Suite is designed, tested and supported in the United States of America. To learn more about Blue Pearl visit http://www.bluepearlsoftware.com.

Press Contact:
Jenn Treiber, Blue Pearl Software, +1- 408.961.0121, x341
jenn.treiber@bluepearlsoftware.com

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Jenn Treiber
Blue Pearl Software
408-961-0121 Ext: 341
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