StreamDSP releases v2.0 update to its sFPDP Gen 3.0 (VITA 17.3) IP

Share Article

StreamDSP announces immediate availability of version 2.0 of its sFPDP Gen 3.0 (VITA 17.3) IP, adding support for Copy Mode, UDB ACK, and latency optimizations.

We provide the industry's most trusted sFPDP Gen 3 IP

The StreamDSP sFPDP IP core is a fully-compliant implementation of the Serial Front Panel Data Port (sFPDP) Gen 3.0 communications standard, as defined by the VITA 17.3-2018 specification. With its latest version 2.0 release, StreamDSP has added support for Copy and Copy/Loop modes of operation as well as User Data Block (UDB) ACK support. Copy/Loop mode allows a single master node to send data through a chain of slave nodes while allowing any node in the chain to assert flow control to halt the flow of data. The UDB ACK feature provides a mechanism for guaranteed delivery where the receive node has the ability to acknowledge receipt of good or bad UDB_IDs back to the transmitter. In addition to these new features, StreamDSP has also optimized the latency for all device families.

The StreamDSP sFPDP Gen 3.0 IP currently supports the following FPGA devices:

Altera Stratix-V, Stratix-IV, and Arria-V
Intel Stratix-10, Arria-10, and Cyclone-10
Xilinx Virtex-6
Xilinx Virtex-7, Kintex-7, and Artix-7
Xilinx Virtex UltraScale and Kintex UltraScale
Xilinx Virtex UltraScale+, Kintex UltraScale+, and Zynq UltraScale+

StreamDSP is committed to supporting VITA 17.3 on ANY transceiver-based FPGA family and they are constantly adding support for more families. The comprehensive installation package provided by StreamDSP provides "ready-to-run" simulations and reference designs targeted to popular development boards for each of the supported FPGA families. This universal vendor support allows StreamDSP customers to quickly and easily verify proper operation both in simulation and hardware, greatly shortening integration time. The wide range of FPGA device support also allows StreamDSP to do extensive compatibility testing between different FPGA families using their own array of development boards. The sFPDP Gen-3 IP core from StreamDSP makes it simple for customers to connect Altera, Intel, Xilinx and Microsemi FPGA devices together with very high bandwidth connections. “We provide the industry's most trusted sFPDP Gen 3 IP” commented Greg Schueller, StreamDSP's Director of Business Development. “Our customers are adopting VITA 17.3 at an exciting rate. VITA 17.3 offers more advanced encoding, multi-lane channel bonding, and improved link status which makes it a clear choice for high-bandwidth remote sensor applications, high performance computing, and low-latency chip-to-chip and backplane links. What's even more exciting is that we're seeing VITA 17.3 adoption on new products as well as 17.1 based upgrade designs,” added Greg.

StreamDSP has structured its IP to give the customer full access to the FPGA transceiver. This means that the StreamDSP sFPDP Gen 3 IP core can be configured by the user to run at any line rate supported by the FPGA device. In addition to the flexible line rate support, the StreamDSP IP can also bond any number of channels together including odd numbers of channels. With its superior link bandwidth and FPGA vendor flexibility, it's easy to see why the StreamDSP sFPDP Gen 3 IP remains a popular choice for FPGA based high-speed interconnect.

More Information
Greg Schueller, Director of Business Development
Tel. +1 (855) DSP-FPGA
Fax. +1 (855) 377-3742
StreamDSP LLC, 2025 Riverside Dr, Columbus, OH, 43221, USA

More information about the Serial FPDP VITA 17.3 Standard can be found at
For more specific information about StreamDSP's IP products, please visit:, or call (855) 377-3742.

About StreamDSP LLC
StreamDSP is an intellectual property (IP) company specializing in video, serial communications, and radar processing solutions for Field Programmable Gate Array (FPGA) devices. Headquartered in Columbus, OH, StreamDSP has over 50 years of combined experience serving the military and commercial markets, and is focused on developing IP and providing custom design services for FPGAs.

Share article on social media or email:

View article via:

Pdf Print

Contact Author

Greg Schueller
+1 (855) 377-3742 Ext: 101
Email >
since: 07/2019
Follow >
Like >
Visit website